module romatantable (MODE, ADDR, DATA);

input [1:0] MODE;
input [2:0] ADDR;
output [7:0] DATA;

wire [1:0] MODE;
wire [2:0] ADDR;
reg [7:0] DATA;

always @ (MODE or ADDR)
begin
	case (MODE)
	2'b01:
		case (ADDR)
		3'b000: DATA = 8'h32;
		3'b001: DATA = 8'h1e;
		3'b010: DATA = 8'h10;
		3'b011: DATA = 8'h08;
		3'b100: DATA = 8'h04;
		3'b101: DATA = 8'h02;
		3'b110: DATA = 8'h01;
		3'b111: DATA = 8'h00;
		endcase
	2'b00:
		case (ADDR)
		3'b000: DATA = 8'h20;
		3'b001: DATA = 8'h10;
		3'b010: DATA = 8'h08;
		3'b011: DATA = 8'h04;
		3'b100: DATA = 8'h02;
		3'b101: DATA = 8'h01;
		3'b110: DATA = 8'h01;
		3'b111: DATA = 8'h00;
		endcase
	2'b11:
		case (ADDR)
		3'b000: DATA = 8'h23;
		3'b001: DATA = 8'h10;
		3'b010: DATA = 8'h08;
		3'b011: DATA = 8'h04;
		3'b100: DATA = 8'h04;
		3'b101: DATA = 8'h02;
		3'b110: DATA = 8'h01;
		3'b111: DATA = 8'h01;
		endcase
	default:
		DATA = 8'hXX;
	endcase
end

endmodule
